FIG. 1 illustrates a prior art fast static NOR gate 15. The fast static NOR gate 15 contains an OR pullup network 10 and an OR pulldown network 20. The OR pullup network 10 receives, as inputs, "n" gate inputs (I.sub.1 -I.sub.n). The OR pullup network 10 contains a plurality of pullup devices 40, 50 and 60, one for each gate input to the fast static NOR gate 15, respectively. The pullup devices 40, 50 and 60 are n-channel field effect transistors (FETs) used as source followers. The source of each n-channel pullup device is coupled to node A, and the drain of each n-channel pullup device is coupled to a source voltage, V.sub.cc. The OR pulldown network 20 contains "n" pulldown devices, 70, 80 and 90, one pulldown device for each gate input, respectively. The pulldown devices 70, 80 and 90 are also n-channel FETs. The source of each n-channel pulldown device is coupled to node B, and the drain of each n-channel pulldown device is coupled to ground.
The fast static NOR gate 15 also contains a complimentary metal oxide semiconductor (CMOS) inverter 22 including a p-channel transistor 25 and a n-channel transistor 30. Furthermore, the fast static NOR gate 15 contains a leaker transistor 35, coupled to node A, and implemented with a n-channel transistor. The source of the leaker transistor 35 is coupled to node A, the drain is coupled to ground, and the gate is coupled to V.sub.cc. The leaker transistor 35 pulls the voltage at node A to a low level logic when the n-channel transistors 40, 50, and 60 are biased to conduct no current.
As shown in FIG. 1, each gate input I.sub.1,I.sub.2, and I.sub.n to the fast static NOR gate 15 is coupled to the gate of both a pullup device 40, 50, and 60 and a pulldown device 70, 80, and 90. In operation, a high logic level on any gate input results in the corresponding n-channel pullup device driving node A to a "weak" high logic voltage. Because the OR pullup network 10 is implemented with n-channel devices, the "weak" high logic voltage generated at node A is due, in part, to the source voltage, V.sub.cc, minus the threshold voltage of the corresponding n-channel pullup device. In other logic networks, the "weak" high logic voltage may be further diminished by a series of n-channel transistor threshold voltages, resulting in an even lower high logic voltage. In addition, the "weak" high logic voltage generated at node A is caused by the conduction of current through the leaker transistor 35.
For the prior art static NOR gate 15, the CMOS inverter 22 is constructed to switch upon sensing the "weak" high voltage. When the "weak" high logic level at node A is input to the CMOS inverter 22, the CMOS inverter 22 generates a low logic level at node B. The low logic level at node B represents the gate output of the NOR logic function.
However, because node A does not attain a full high logic voltage, the p-channel transistor 25 is not completely turned off. Consequently, because the p-channel transistor 25 is still conducting current, the n-channel transistor 30 continues to sink current resulting in dissipation of power. Because the transistors 25 and 30 of CMOS inverter 22 drive CMOS compatible outputs, the power dissipation is significant. In addition, the n-channel transistor 30 is properly sized in order to sense the "weak" high at node A so as to sink enough current to pull node B to a low logic level.
If all the gate inputs I.sub.1,I.sub.2, and I.sub.n to the fast static NOR gate 15 are a low logic level, then the leaker transistor 35 pulls node A to a low logic level. Consequently, the CMOS inverter 22 generates a high logic level at node B. The size of the n-channel leaker transistor 35 is large enough to pull node A low when all n-channel pullup devices are turned off, but is small enough to permit a high logic level at node A when one of the n-channel pullup transistors is turned on. The n-channel transistor 30 is appropriately sized in order to turn off at the low logic level generated at node A from the conduction of current through the leaker transistor 35.
For applications requiring a low source voltage, the fast static NOR gate 15 does not scale accordingly because the n-channel pullup transistors 40, 50, 60 exhibit approximately a 0.5 to 0.6 threshold voltage. Because of this minimum threshold voltage, the sizing of the p-channel transistor 25 and n-channel transistor 30 is crucial. In addition, operating at a low source voltage increases the power dissipation through the CMOS inverter 22. Consequently, it is desirable to construct a fast static gate that minimizes power dissipation.